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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21357-2E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F03SL
s DESCRIPTION
The Fujitsu MB15F03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1750 MHz and a 600 MHz prescalers. The 1750 MHz prescaler, and 600 MHz prescaler have a dual modulus division ratio of 64/65 or 128/129 and 8/9 or 16/17 enabling pulse swallow operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15F03SL uses the latest BiCMOS process. As a result, the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5 mA or 6 mA. The charge pump current is selectable by serial data. MB15F03SL is ideally suited for wireless mobile communications, such as GSM and PDC.
s FEATURES
* High frequency operation: RF synthesizer: 1750 MHz max IF synthesizer: 600 MHz max * Low power supply voltage: VCC = 2.4 to 3.6 V * Ultra Low power supply current: ICC = 3.5 mA typ. (VCC = 2.7 V, Ta = +25C, in IF, RF locking state) ICC = 4.0 mA typ. (VCC = 3.0 V, Ta = +25C, in IF, RF locking state) * Direct power saving function: Power supply current in power saving mode Typ. 0.1 A (VCC = 3V, Ta = +25C), Max. 10 A (VCC = 3V) * Dual modulus prescaler: 1750 MHz prescaler (64/65 or 128/129)/600 MHz prescaler (8/9 or 16/17) * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Software selectable charge pump current * On-chip phase control for phase comparator * Operating temperature: Ta = -40 to +85C * Pin compatible with MB15F03, MB15F03L
s PACKAGES
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M04) 1
MB15F03SL
s PIN ASSIGNMENTS
16-pin SSOP
GNDRF OSCIN GNDIF finIF VCCIF LD/fout PSIF DOIF 1 2 3 4 5 6 7 8 16 15 14 TOP 13 VIEW 12 11 10 9 Clock Data LE OSCIN finRF VCCRF XfinRF PSRF DORF GNDIF finIF VCCIF LD/fout PSIF GNDRF Clock 1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 Data LE finRF VCCRF XfinRF PSRF
16-pad BCC
DOIF DORF
(FPT-16P-M05)
(LCC-16P-M04)
2
MB15F03SL
s PIN DESCRIPTION
Pin no. SSOP 1 2 3 4 5 BCC 16 1 2 3 4 Pin name GNDRF OSCIN GNDIF finIF VCCIF I/O - I - I - Ground for RF-PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. Connection to an external VCO should be via AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS bit = "H" ; outputs fout signal LDS bit = "L" ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at "L" during Power-ON. (Open is prohibited.) PSIF = "H" ; Normal mode PSIF = "L" ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at "L" during Power-ON. (Open is prohibited.) PSRF = "H" ; Normal mode PSRF = "L" ; Power saving mode Prescaler complementary input for the RE-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RF-PLL is lost. Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. Load enable signal inpunt (with a schmitt trigger input buffer.) When the LE bit is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. Serial data input (with a schmitt trigger input buffer.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in the serial data. Clock input for the 23-bit shift register (with a schmitt trigger input buffer.) One bit of data is shifted into the shift register on a rising edge of the clock. Descriptions
6
5
LD/fout
O
7
6
PSIF
I
8
7
DoIF
O
9
8
DoRF
O
10
9
PSRF
I
11 12 13 14
10 11 12 13
XfinRF VCCRF finRF LE
I - I I
15
14
Data
I
16
15
Clock
I
3
MB15F03SL
s BLOCK DIAGRAM
VCCIF GNDIF (4) 5 3 (2)
PSIF 7 (6)
Intermittent mode control (IF-PLL)
3-bit latch
LDS SWIF FCIF
7-bit latch
Binary 7-bit swallow counter (IF-PLL)
11-bit latch
Binary 11-bit programmable counter (IF-PLL)
fpIF
Phase comp. (IF-PLL)
Charge pump. Current (IF-PLL) Switch
8 DoIF (7)
finIF 4 (3)
Prescaler (IF-PLL) 8/9, 16/17
Lock Det. (IF-PLL)
2-bit latch
14-bit latch
Binary 14-bit programmable ref. counter (IF-PLL)
1-bit latch
C/P setting current
LDIF
T1
T2
frIF OSCIN 2 (1) frRF OR T1 T2
Binary 14-bit programmable ref. counter (RF-PLL) C/P setting current
AND
Selector
2-bit latch
14-bit latch
1-bit latch
LD frIF frRF fpIF fpRF Lock Det. (RF-PLL)
6 LD/ (5) fout
(12) finRF 13 XfinRF 11 (10)
Prescaler (RF-PLL) 64/65, 128/129
PSRF 10 (9)
Intermittent mode control (RF-PLL)
LDS SWRF FCRF
Binary 7-bit swallow counter (RF-PLL)
Binary 11-bit programmable counter (RF-PLL)
Phase comp. (RF-PLL) fpRF
Charge Current pump. Switch (RF-PLL)
9 DoRF (8)
3-bit latch
7-bit latch
11-bit latch
LE 14 (13) (14) Data 15 Clock 16 (15)
Schmitt circuit
Latch selector
Schmitt circuit Schmitt circuit
CC NN 12
23-bit shift register
(11)12 1 (16) VCCRF GNDRF
O -- SSOP ( ) -- BCC
4
MB15F03SL
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VI VO Tstg Rating Min. -0.5 -0.5 GND -55 Max. +4.0 VCC +0.5 VCC +125 Unit V V V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VI Ta Value Min. 2.4 GND -40 Typ. 3.0 - - Max. 3.6 VCC +85 Unit V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F03SL
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter Symbol ICCIF*1 Power supply current*
1
Condition finIF = 223.15 MHz finRF = 1750 MHz VCCIF = 2.7 V (VCCIF = 3.0 V) VCCRF = 2.7 V (VCCRF = 3.0 V)
Value Min. - - - - 50 100 Typ. 1.2 (1.5) 2.3 (2.5) 0.1*2 0.1* - - - - -
2
Max. - - 10 10 600 1750 40 +2 +2 VCC
Unit mA mA A A MHz MHz MHz dBm dBm Vp-p V
ICCRF*1 Power saving current finIF Operating frequency
*3 *3
IPSIF IPSRF finIF finRF fosc PfinIF VOSC VIH VIL VIH VIL IIH*4 IIL*4 IIH IIL
*4
PSIF = PSRF = "L" PSIF = PSRF = "L" IF PLL RF PLL - IF PLL, 50 system - Schmitt trigger input Schmitt trigger input - - - - - - VCC = 3 V, IOH = -1 mA VCC = 3 V, IOL = 1 mA VCC = 3 V, IDOH = -0.5 mA VCC = 3 V, IDOL = 0.5 mA VCC = 3 V, VOFF = 0.5 V to VCC -0.5V VCC = 3 V VCC = 3 V VCC = 3 V, VDOH = VCC/2, Ta = +25C CS bit = "H" CS bit = "L"
finRF finIF
OSCIN
*8
3 -15 -15 0.5 VCC x 0.7 + 0.4 - VCC x 0.7 - -1.0 -1.0 0 -100 VCC - 0.4 - VCC - 0.4 - - -1.0 - - -
Input sensitivity
finRF OSCIN
PfinRF RF PLL, 50 system
"H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H" level output current "L" level output current "H" level output current
Data, Clock, LE, PS Data, Clock, LE, PS OSCIN LD/fout DoIF DoRF DoIF DoRF LD/fout DoIF DoRF
- - - - - - - - - - - - - - - -6.0 -1.5
- VCC x 0.3 - 0.4 - VCC x 0.3 +1.0 +1.0 +100 0 - 0.4 - 0.4 2.5 - 1.0 - - mA
V A A V V nA mA
VOH VOL VDOH VDOL IOFF IOH*4 IDOL*4 IDOH*4
(Continued)
6
MB15F03SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter "L" level output current DoIF DoRF Symbol IDOL Condition VCC = 3 V, VDOL= VCC/2, Ta = +25C CS bit = "H" CS bit = "L" Value Min. - - - - - Typ. 6.0 1.5 3 10 10 Max. - - - - - mA % % % Unit
IDOL/IDOH IDOMT*5 VDO = VCC/2 Charge pump current rate vs VDO vs Ta *1: *2: *3: *4: *5: *6: *7: *8: IDOVD
*6
0.5 V VDO VCC - 0.5 V -40C Ta + 85C, VDO = VCC/2
IDOTA*7
Conditions; fosc = 12 MHz, Ta = +25C, in locking state. VCCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25C, in power saving state. AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency. The symbol "-" (minus) means direction of current flow. VCC = 3.0 V, Ta = +25C (|I3| - |I4|)/[(|I3| + |I4|)]/2] x 100(%) VCC = 3.0 V, Ta = +25C [(|I2| - |I1|)/2]/[(|I1| + |I2|)/2] x 100(%) (Applied to each IDOL, IDOH) VCC = 3.0 V, [|IDO(85C) - IDO(-40C)|/2]/[IDO(85C) + IDO(-40C)|/2] x 100(%) (Applied to each IDOL, IDOH) Prescaler divide ratio C/P current fin operating frequency Input sensitivity 16/17 1.5 mA mode 50 MHz fin 600 MHz -15 dBm 6.0 mA mode 50 MHz fin 300 MHz -15 dBm 300 MHz < fin 600 MHz -10 dBm 8/9 1.5 mA mode 50 MHz fin 300 MHz -15 dBm 300 MHz < fin 600 MHz* -15 dBm 6.0 mA mode 50 MHz fin 300 MHz -15 dBm 300 MHz < fin 600 MHz* -10 dBm
* : VCC = 3.0 V to 3.6 V at 600 MHz
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 VCC/2 VCC - 0.5 V VCC
Charge Pump Output voltage (V)
7
MB15F03SL
s FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) M : Preset divide ratio of dual modulus prescaler (8or 16 for IF-PLL, 64 or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Reference oscillation frequency R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table.1 Control Bit
Control bit CN1 L H L H CN2 L L H H Destination of serial data The programmable reference counter for the IF-PLL The programmable reference counter for the RF-PLL The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 T 1
4 T 2
5 R 1
6 R 2
7 R 3
8 R 4
9 R 5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 R 6 R 7 R 8 R 9 RRRRR 10 11 12 13 14 C S
X
X
X
X
CN1,2 R1 to R14 T1, 2 CS X
: Control bit [Table. 1] : Divide ratio setting bit for the programmable reference counter (5 to 16,383)[Table. 2] : Test purpose bit [Table. 3] : Charge pump currnet select bit [Table. 9] : Dummy bits (Set "0" or "1")
NOTE: Data input with MSB first.
8
MB15F03SL
Programmable Counter
LSB MSB Data Flow
1 C N 1
2 C N 2
3 L D S
4 S W
IF/RF
5 F C
IF/RF
6 A 1
7 A 2
8 A 3
9 A 4
10 A 5
11 A 6
12 A 7
13 N 1
14 N 2
15 N 3
16 N 4
17 N 5
18 N 6
19 N 7
20 N 8
21 N 9
22 N 10
23 N 11
CNT1, 2 : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) SWIF/RF : Divide ratio setting bits for the prescaler (8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF) FCIF/RF : Phase control bit for the phase detector (IF: FCIF, RF: FCRF) LDS : LD/fout signal select bit NOTE: Data input with MSB first.
[Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 0 1 1 R 2 1 0 1 R 1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table.3 Test Purpose Bit Setting
T 1 L H L H T 2 L L H H LD/fout pin state Outputs frIF Outputs frRF Outputs fpIF Outputs fpRF
9
MB15F03SL
Table.4 Brinary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 0 1 1 N 2 1 0 1 N 1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table.5 Brinary 7-bit Swallow Counter Data Setting
Divide ratio (N) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Note: Divide ratio (A) range = 0 to 127
Table.6 Prescaler Data Setting
SW = "H" Prescaler divide ratio IF-PLL RF-PLL 8/9 64/65 SW = "L" 16/17 128/129
Table.7 Phase Comparator Phase Switching Data Setting
FCIF, RE = H DoIF, RF fr > fp fr = fp fr < fp VCO polarity H Z L (1) L Z H (2)
(2)
FCIF, RE = L
(1)
VCO Output Frequency
Note: Z = High-impedance Depending upon the VCO and LPF polarity, FC bit should be set.
LPF Output Voltage
Table.8 LD/fout Output Select Data Setting
LDS H L LD/fout output signal fout (frIF/RF, fpIF/RF) signals LD signal
10
MB15F03SL
Table.9 Charge Pump Current Setting
CS H L Current value 6.0 mA 1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit) Table.10 PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Note: Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s. PS pin must be set "L" for Power-ON.
OFF tV 1 s
ON
VCC Clock Data LE
tps 100 ns PS (1) (2) (3)
(1) PS = L (power saving mode) at Power-ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS : L H) 100 ns later after setting serial data.
11
MB15F03SL
s SERIAL DATA INPUT TIMING
1st data 2nd data
Control bit
Invalid data
Data
MSB
LSB
Clock t1 t7 LE t4 t5 t2 t3 t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
t1 t2 t3 t4
Min.
20 20 30 30
Typ.
- - - -
Max.
- - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min.
100 20 100
Typ.
- - -
Max.
- - -
Unit
ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
12
MB15F03SL
s PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
DOIF/RF
H L
Z
(FC bit = Low)
DOIF/RF
Z
LD Output Logic Table
IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
LD output H L L L
Notes: * Phase error detection range = -2 to +2 * Pulses on DoIF/RF signals are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCin input frequency as follows. tWU > 2/fosc: i. e. tWU > 156.3 ns when foscin = 12.8 MHz tWU < 4/fosc: i. e. tWL < 312.5 ns when foscin = 12.8 MHz
13
MB15F03SL
s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
fout Oscilloscope VCCIF
0.1F S*G 1000 pF 50 1000 pF 50 S*G
DOIF 8
PSIF 7
LD/fout 6
VCCIF 5
finIF 4
GNDIF 3
OSCIN 2
GNDRF 1
GND
MB15F03SL 9 DORF 10 PSRF 11 XfinRF 12 VCCRF 13 finRF 14 LE 15 Data 16 Clock
S*G 50
1000 pF Controller (divide ratio setting) VCCRF 1000 pF
0.1F
Note: SSOP-16
14
MB15F03SL
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF PLL input sensitivity - Input frequency 10 5 Input sensitivity PfinRF (dBm) 0 -5 -10 -15 -20 -25 -30 -35 -40 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 Input frequency finRF (MHz)
,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
Ta = +25 C SPEC VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V
IF PLL input sensitivity - Input frequency 10 5 Input sensitivity PfinIF (dBm) 0 -5 -10 -15 -20 -25 -30 -35 -40 0 200 400 600 800 1000 Input frequency finIF (MHz) Ta = +25 C
,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
SPEC VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V
15
MB15F03SL
2. OSCIN input sensitivity
10 Input sensitivity VOSC (dBm) 0 -10 -20 -30 -40 -50
,,,, ,,,,
SPEC
Input sensitivity - Input frequency Ta = +25 C
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 0 20 40 60 80 100 120 140 160 180 200 220 240
Input frequency fOSC (MHz)
16
MB15F03SL
3. Do output current (RF PLL) 1.5 mA mode
IDO - VDO Ta = +25 C VCC = 3.0 V
10.00
Charge pump output current IDO (mA)
2.000 /div 0
IDOL
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
6.0 mA mode
IDO - VDO Ta = +25 C VCC = 3.0 V IDOL
10.00
Charge pump output current IDO (mA)
2.000 /div 0
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
17
MB15F03SL
4. Do output current (IF PLL) 1.5 mA mode
IDO - VDO Ta = +25 C VCC = 3.0 V
10.00
Change pump output current IDO (mA)
2.000 /div 0
IDOL
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
6.0 mA mode
IDO - VDO Ta = +25 C VCC = 3.0 V IDOL 2.000 /div 0
10.00
Charge pump output current IDO (mA)
IDOH
-10.00 0 .6000/div Charge pump output voltage VDO (V) 4.800
18
MB15F03SL
5. fin input impedance
finRF input impedance
1 : 23.281 -162.47 500 MHz 2 : 11.291 -59.674 1 GHz 3 : 16.957 -13.534 1.5 GHz 4 : 22.478 -3.9443 1.8 GHz 3 1
4
2
START 100.000 000 MHz
STOP 1 800.000 000 MHz
finIF input impedance
1 : 897.31 -1.0259 k 50 MHz 2 : 98.781 -429.3 200 MHz 3 : 29.75 -216.69 400 MHz 1 2 4 : 16.781 -139.35 600 MHz
4
3
START 50.000 000 MHz
STOP 600.000 000 MHz
19
MB15F03SL
6. OSCIN input impedance
OSCIN input impedance
1 : 9.451 k -3.1875 k 3 MHz 2 : 4.7255 k -5.1685 k 10 MHz 3 : 1.6918 k -3.8045 k 4 20 MHz 1 3 2 4 : 463.75 -2.1069 k 40 MHz
START 3.000 000 MHz
STOP 40.000 000 MHz
20
MB15F03SL
s APPLICATION EXAMPLE
OUTPUT
VCO
LPF
1000 pF
3V 0.1F 1000 pF
From a controller
Clock 16 Data 15 XfinRF 11
LE 14
finRF 13
VCCRF 12
PSRF 10
DoRF 9
MB15F03SL
1 GNDRF
2 OSCIN
3 GNDIF
4 finIF
5 VCCIF
6 LD/fout
7 PSIF
8 DoIF
3V 1000 pF TCXO 1000 pF 0.1F LockDet
OUTPUT
VCO
LPF
Note: SSOP-16
s USAGE PRECAUTIONS
(1) VccRF must equa VccIF . Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF and VCCIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Tum off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device.
21
MB15F03SL
s ORDERING INFORMATION
Part number MB15F03SLPFV1 MB15F03SLPV1 Package 16-pin, plastic SSOP (FPT-16P-M05) 16-pad, plastic BCC (LCC-16P-M04) Remarks
22
MB15F03SL
s PACKAGE DIMENSIONS
16-pin plastic SSOP (FPT-16P-M05) * : These dimensions do not include resin protrusion.
* 5.000.10(.197.004)
1.25 -0.10 .049 -.004
+0.20 +.008
(Mounting height)
0.10(.004)
INDEX
* 4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches)
(Continued)
23
MB15F03SL
(Continued)
16-pad plastic BCC (LCC-16P-M04)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
0.80(.031) REF
INDEX AREA
4.200.10 (.165.004)
3.25(.128) TYP "A" "B" 1.55(.061) REF
0.400.10 (.016.004)
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF Details of "B" part 0.600.10 (.024.004)
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16015S-1C-1
Dimensions in mm (inches)
24
MB15F03SL
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9904 (c) FUJITSU LIMITED Printed in Japan
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